Fitter report for DE0_NANO
Mon Jun 19 20:10:14 2017
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Ignored Assignments
  7. Incremental Compilation Preservation Summary
  8. Incremental Compilation Partition Settings
  9. Incremental Compilation Placement Preservation
 10. Pin-Out File
 11. Fitter Resource Usage Summary
 12. Fitter Partition Statistics
 13. Input Pins
 14. Output Pins
 15. Bidir Pins
 16. Dual Purpose and Dedicated Pins
 17. I/O Bank Usage
 18. All Package Pins
 19. Fitter Resource Utilization by Entity
 20. Delay Chain Summary
 21. Pad To Core Delay Chain Fanout
 22. Control Signals
 23. Global & Other Fast Signals
 24. Routing Usage Summary
 25. LAB Logic Elements
 26. LAB-wide Signals
 27. LAB Signals Sourced
 28. LAB Signals Sourced Out
 29. LAB Distinct Inputs
 30. I/O Rules Summary
 31. I/O Rules Details
 32. I/O Rules Matrix
 33. Fitter Device Options
 34. Operating Settings and Conditions
 35. Fitter Messages
 36. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Mon Jun 19 20:10:14 2017       ;
; Quartus Prime Version              ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
; Revision Name                      ; DE0_NANO                                    ;
; Top-level Entity Name              ; DE0_NANO                                    ;
; Family                             ; Cyclone IV E                                ;
; Device                             ; EP4CE22F17C6                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 82 / 22,320 ( < 1 % )                       ;
;     Total combinational functions  ; 82 / 22,320 ( < 1 % )                       ;
;     Dedicated logic registers      ; 47 / 22,320 ( < 1 % )                       ;
; Total registers                    ; 47                                          ;
; Total pins                         ; 87 / 154 ( 56 % )                           ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0 / 608,256 ( 0 % )                         ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                             ;
; Total PLLs                         ; 0 / 4 ( 0 % )                               ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; EP4CE22F17C6                          ;                                       ;
; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
; Use smart compilation                                                      ; Off                                   ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------+
; I/O Assignment Warnings               ;
+--------------+------------------------+
; Pin Name     ; Reason                 ;
+--------------+------------------------+
; LED[0]       ; Missing drive strength ;
; LED[1]       ; Missing drive strength ;
; LED[2]       ; Missing drive strength ;
; LED[3]       ; Missing drive strength ;
; LED[4]       ; Missing drive strength ;
; LED[5]       ; Missing drive strength ;
; LED[6]       ; Missing drive strength ;
; LED[7]       ; Missing drive strength ;
; GPIO_0_D[0]  ; Missing drive strength ;
; GPIO_0_D[1]  ; Missing drive strength ;
; GPIO_0_D[2]  ; Missing drive strength ;
; GPIO_0_D[3]  ; Missing drive strength ;
; GPIO_0_D[4]  ; Missing drive strength ;
; GPIO_0_D[6]  ; Missing drive strength ;
; GPIO_0_D[8]  ; Missing drive strength ;
; GPIO_0_D[10] ; Missing drive strength ;
; GPIO_0_D[12] ; Missing drive strength ;
; GPIO_0_D[14] ; Missing drive strength ;
; GPIO_0_D[16] ; Missing drive strength ;
; GPIO_0_D[18] ; Missing drive strength ;
; GPIO_0_D[20] ; Missing drive strength ;
; GPIO_0_D[22] ; Missing drive strength ;
; GPIO_0_D[24] ; Missing drive strength ;
; GPIO_0_D[25] ; Missing drive strength ;
; GPIO_0_D[26] ; Missing drive strength ;
; GPIO_0_D[27] ; Missing drive strength ;
; GPIO_0_D[28] ; Missing drive strength ;
; GPIO_0_D[29] ; Missing drive strength ;
; GPIO_0_D[30] ; Missing drive strength ;
; GPIO_0_D[31] ; Missing drive strength ;
; GPIO_0_D[32] ; Missing drive strength ;
; GPIO_0_D[33] ; Missing drive strength ;
; GPIO_1_D[0]  ; Missing drive strength ;
; GPIO_1_D[1]  ; Missing drive strength ;
; GPIO_1_D[2]  ; Missing drive strength ;
; GPIO_1_D[3]  ; Missing drive strength ;
; GPIO_1_D[4]  ; Missing drive strength ;
; GPIO_1_D[5]  ; Missing drive strength ;
; GPIO_1_D[6]  ; Missing drive strength ;
; GPIO_1_D[7]  ; Missing drive strength ;
; GPIO_1_D[8]  ; Missing drive strength ;
; GPIO_1_D[9]  ; Missing drive strength ;
; GPIO_1_D[10] ; Missing drive strength ;
; GPIO_1_D[11] ; Missing drive strength ;
; GPIO_1_D[12] ; Missing drive strength ;
; GPIO_1_D[13] ; Missing drive strength ;
; GPIO_1_D[14] ; Missing drive strength ;
; GPIO_1_D[15] ; Missing drive strength ;
; GPIO_1_D[16] ; Missing drive strength ;
; GPIO_1_D[17] ; Missing drive strength ;
; GPIO_1_D[18] ; Missing drive strength ;
; GPIO_1_D[19] ; Missing drive strength ;
; GPIO_1_D[20] ; Missing drive strength ;
; GPIO_1_D[21] ; Missing drive strength ;
; GPIO_1_D[22] ; Missing drive strength ;
; GPIO_1_D[23] ; Missing drive strength ;
; GPIO_1_D[24] ; Missing drive strength ;
; GPIO_1_D[25] ; Missing drive strength ;
; GPIO_1_D[26] ; Missing drive strength ;
; GPIO_1_D[27] ; Missing drive strength ;
; GPIO_1_D[28] ; Missing drive strength ;
; GPIO_1_D[29] ; Missing drive strength ;
; GPIO_1_D[30] ; Missing drive strength ;
; GPIO_1_D[31] ; Missing drive strength ;
; GPIO_1_D[32] ; Missing drive strength ;
; GPIO_1_D[33] ; Missing drive strength ;
; GPIO_0_D[5]  ; Missing drive strength ;
; GPIO_0_D[7]  ; Missing drive strength ;
; GPIO_0_D[9]  ; Missing drive strength ;
; GPIO_0_D[11] ; Missing drive strength ;
; GPIO_0_D[13] ; Missing drive strength ;
; GPIO_0_D[15] ; Missing drive strength ;
; GPIO_0_D[17] ; Missing drive strength ;
; GPIO_0_D[19] ; Missing drive strength ;
; GPIO_0_D[21] ; Missing drive strength ;
; GPIO_0_D[23] ; Missing drive strength ;
+--------------+------------------------+


+-----------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                           ;
+--------------+----------------+--------------+---------------+---------------+----------------+
; Name         ; Ignored Entity ; Ignored From ; Ignored To    ; Ignored Value ; Ignored Source ;
+--------------+----------------+--------------+---------------+---------------+----------------+
; Location     ;                ;              ; ADC_CS_N      ; PIN_A10       ; QSF Assignment ;
; Location     ;                ;              ; ADC_SADDR     ; PIN_B10       ; QSF Assignment ;
; Location     ;                ;              ; ADC_SCLK      ; PIN_B14       ; QSF Assignment ;
; Location     ;                ;              ; ADC_SDAT      ; PIN_A9        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[0]  ; PIN_P2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[10] ; PIN_N2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[11] ; PIN_N1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[12] ; PIN_L4        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[1]  ; PIN_N5        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[2]  ; PIN_N6        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[3]  ; PIN_M8        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[4]  ; PIN_P8        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[5]  ; PIN_T7        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[6]  ; PIN_N8        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[7]  ; PIN_T6        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[8]  ; PIN_R1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_ADDR[9]  ; PIN_P1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_BA[0]    ; PIN_M7        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_BA[1]    ; PIN_M6        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_CAS_N    ; PIN_L1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_CKE      ; PIN_L7        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_CLK      ; PIN_R4        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_CS_N     ; PIN_P6        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQM[0]   ; PIN_R6        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQM[1]   ; PIN_T5        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[0]    ; PIN_G2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[10]   ; PIN_T3        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[11]   ; PIN_R3        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[12]   ; PIN_R5        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[13]   ; PIN_P3        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[14]   ; PIN_N3        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[15]   ; PIN_K1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[1]    ; PIN_G1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[2]    ; PIN_L8        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[3]    ; PIN_K5        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[4]    ; PIN_K2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[5]    ; PIN_J2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[6]    ; PIN_J1        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[7]    ; PIN_R7        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[8]    ; PIN_T4        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_DQ[9]    ; PIN_T2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_RAS_N    ; PIN_L2        ; QSF Assignment ;
; Location     ;                ;              ; DRAM_WE_N     ; PIN_C2        ; QSF Assignment ;
; Location     ;                ;              ; EPCS_ASDO     ; PIN_C1        ; QSF Assignment ;
; Location     ;                ;              ; EPCS_DATA0    ; PIN_H2        ; QSF Assignment ;
; Location     ;                ;              ; EPCS_DCLK     ; PIN_H1        ; QSF Assignment ;
; Location     ;                ;              ; EPCS_NCSO     ; PIN_D2        ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[0]     ; PIN_A14       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[10]    ; PIN_F14       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[11]    ; PIN_G16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[12]    ; PIN_G15       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[1]     ; PIN_B16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[2]     ; PIN_C14       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[3]     ; PIN_C16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[4]     ; PIN_C15       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[5]     ; PIN_D16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[6]     ; PIN_D15       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[7]     ; PIN_D14       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[8]     ; PIN_F15       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2[9]     ; PIN_F16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2_IN[0]  ; PIN_E15       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2_IN[1]  ; PIN_E16       ; QSF Assignment ;
; Location     ;                ;              ; GPIO_2_IN[2]  ; PIN_M16       ; QSF Assignment ;
; Location     ;                ;              ; G_SENSOR_CS_N ; PIN_G5        ; QSF Assignment ;
; Location     ;                ;              ; G_SENSOR_INT  ; PIN_M2        ; QSF Assignment ;
; Location     ;                ;              ; I2C_SCLK      ; PIN_F2        ; QSF Assignment ;
; Location     ;                ;              ; I2C_SDAT      ; PIN_F1        ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; ADC_CS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; ADC_SADDR     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; ADC_SCLK      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; ADC_SDAT      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[10] ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[11] ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[12] ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[2]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[3]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[4]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[5]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[6]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[7]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[8]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_ADDR[9]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_BA[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_BA[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_CAS_N    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_CKE      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_CLK      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_CS_N     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQM[0]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQM[1]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[10]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[11]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[13]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[14]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[15]   ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_DQ[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_RAS_N    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; DRAM_WE_N     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; EPCS_ASDO     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; EPCS_DATA0    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; EPCS_DCLK     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; EPCS_NCSO     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[10]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[11]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[12]    ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[8]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2[9]     ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2_IN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2_IN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; GPIO_2_IN[2]  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; G_SENSOR_CS_N ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; G_SENSOR_INT  ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; I2C_SCLK      ; 3.3-V LVTTL   ; QSF Assignment ;
; I/O Standard ; DE0_NANO       ;              ; I2C_SDAT      ; 3.3-V LVTTL   ; QSF Assignment ;
+--------------+----------------+--------------+---------------+---------------+----------------+


+--------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                     ;
+---------------------+--------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+--------------------+----------------------------+--------------------------+
; Placement (by node) ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 373 ) ; 0.00 % ( 0 / 373 )         ; 0.00 % ( 0 / 373 )       ;
;     -- Achieved     ; 0.00 % ( 0 / 373 ) ; 0.00 % ( 0 / 373 )         ; 0.00 % ( 0 / 373 )       ;
;                     ;                    ;                            ;                          ;
; Routing (by net)    ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+--------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 373 )    ; N/A                     ; Source File       ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.pin.


+---------------------------------------------------------------------+
; Fitter Resource Usage Summary                                       ;
+---------------------------------------------+-----------------------+
; Resource                                    ; Usage                 ;
+---------------------------------------------+-----------------------+
; Total logic elements                        ; 82 / 22,320 ( < 1 % ) ;
;     -- Combinational with no register       ; 35                    ;
;     -- Register only                        ; 0                     ;
;     -- Combinational with a register        ; 47                    ;
;                                             ;                       ;
; Logic element usage by number of LUT inputs ;                       ;
;     -- 4 input functions                    ; 17                    ;
;     -- 3 input functions                    ; 3                     ;
;     -- <=2 input functions                  ; 62                    ;
;     -- Register only                        ; 0                     ;
;                                             ;                       ;
; Logic elements by mode                      ;                       ;
;     -- normal mode                          ; 40                    ;
;     -- arithmetic mode                      ; 42                    ;
;                                             ;                       ;
; Total registers*                            ; 47 / 23,018 ( < 1 % ) ;
;     -- Dedicated logic registers            ; 47 / 22,320 ( < 1 % ) ;
;     -- I/O registers                        ; 0 / 698 ( 0 % )       ;
;                                             ;                       ;
; Total LABs:  partially or completely used   ; 11 / 1,395 ( < 1 % )  ;
; Virtual pins                                ; 0                     ;
; I/O pins                                    ; 87 / 154 ( 56 % )     ;
;     -- Clock pins                           ; 7 / 7 ( 100 % )       ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
;                                             ;                       ;
; Global signals                              ; 1                     ;
; M9Ks                                        ; 0 / 66 ( 0 % )        ;
; Total block memory bits                     ; 0 / 608,256 ( 0 % )   ;
; Total block memory implementation bits      ; 0 / 608,256 ( 0 % )   ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )       ;
; PLLs                                        ; 0 / 4 ( 0 % )         ;
; Global clocks                               ; 1 / 20 ( 5 % )        ;
; JTAGs                                       ; 0 / 1 ( 0 % )         ;
; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
; Oscillator blocks                           ; 0 / 1 ( 0 % )         ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
; Average interconnect usage (total/H/V)      ; 0.1% / 0.1% / 0.0%    ;
; Peak interconnect usage (total/H/V)         ; 0.2% / 0.3% / 0.2%    ;
; Maximum fan-out                             ; 46                    ;
; Highest non-global fan-out                  ; 20                    ;
; Total fan-out                               ; 483                   ;
; Average fan-out                             ; 1.30                  ;
+---------------------------------------------+-----------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                         ;
+---------------------------------------------+----------------------+--------------------------------+
; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
+---------------------------------------------+----------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                  ; Low                            ;
;                                             ;                      ;                                ;
; Total logic elements                        ; 82 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % )              ;
;     -- Combinational with no register       ; 35                   ; 0                              ;
;     -- Register only                        ; 0                    ; 0                              ;
;     -- Combinational with a register        ; 47                   ; 0                              ;
;                                             ;                      ;                                ;
; Logic element usage by number of LUT inputs ;                      ;                                ;
;     -- 4 input functions                    ; 17                   ; 0                              ;
;     -- 3 input functions                    ; 3                    ; 0                              ;
;     -- <=2 input functions                  ; 62                   ; 0                              ;
;     -- Register only                        ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Logic elements by mode                      ;                      ;                                ;
;     -- normal mode                          ; 40                   ; 0                              ;
;     -- arithmetic mode                      ; 42                   ; 0                              ;
;                                             ;                      ;                                ;
; Total registers                             ; 47                   ; 0                              ;
;     -- Dedicated logic registers            ; 47 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % )              ;
;     -- I/O registers                        ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Total LABs:  partially or completely used   ; 11 / 1395 ( < 1 % )  ; 0 / 1395 ( 0 % )               ;
;                                             ;                      ;                                ;
; Virtual pins                                ; 0                    ; 0                              ;
; I/O pins                                    ; 87                   ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )      ; 0 / 132 ( 0 % )                ;
; Total memory bits                           ; 0                    ; 0                              ;
; Total RAM block bits                        ; 0                    ; 0                              ;
; Clock control block                         ; 1 / 24 ( 4 % )       ; 0 / 24 ( 0 % )                 ;
;                                             ;                      ;                                ;
; Connections                                 ;                      ;                                ;
;     -- Input Connections                    ; 68                   ; 0                              ;
;     -- Registered Input Connections         ; 0                    ; 0                              ;
;     -- Output Connections                   ; 68                   ; 0                              ;
;     -- Registered Output Connections        ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Internal Connections                        ;                      ;                                ;
;     -- Total Connections                    ; 483                  ; 0                              ;
;     -- Registered Connections               ; 112                  ; 0                              ;
;                                             ;                      ;                                ;
; External Connections                        ;                      ;                                ;
;     -- Top                                  ; 136                  ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Partition Interface                         ;                      ;                                ;
;     -- Input Ports                          ; 11                   ; 0                              ;
;     -- Output Ports                         ; 8                    ; 0                              ;
;     -- Bidir Ports                          ; 68                   ; 0                              ;
;                                             ;                      ;                                ;
; Registered Ports                            ;                      ;                                ;
;     -- Registered Input Ports               ; 0                    ; 0                              ;
;     -- Registered Output Ports              ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Port Connectivity                           ;                      ;                                ;
;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
;     -- Input Ports with no Source           ; 0                    ; 0                              ;
;     -- Output Ports with no Source          ; 0                    ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
+---------------------------------------------+----------------------+--------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                                    ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; CLOCK_50     ; R8    ; 3        ; 27           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; GPIO_0_IN[0] ; A8    ; 8        ; 25           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; GPIO_0_IN[1] ; B8    ; 8        ; 25           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; GPIO_1_IN[0] ; T9    ; 4        ; 27           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; GPIO_1_IN[1] ; R9    ; 4        ; 27           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; KEY[0]       ; J15   ; 5        ; 53           ; 14           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; KEY[1]       ; E1    ; 1        ; 0            ; 16           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; SW[0]        ; M1    ; 2        ; 0            ; 16           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; SW[1]        ; T8    ; 3        ; 27           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; SW[2]        ; B9    ; 7        ; 25           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; SW[3]        ; M15   ; 5        ; 53           ; 17           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; LED[0] ; A15   ; 7        ; 38           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[1] ; A13   ; 7        ; 49           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[2] ; B13   ; 7        ; 49           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[3] ; A11   ; 7        ; 40           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[4] ; D1    ; 1        ; 0            ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[5] ; F3    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[6] ; B1    ; 1        ; 0            ; 28           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LED[7] ; L3    ; 2        ; 0            ; 10           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
; GPIO_0_D[0]  ; D3    ; 8        ; 1            ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[10] ; B6    ; 8        ; 16           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[11] ; A6    ; 8        ; 16           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[12] ; B7    ; 8        ; 18           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[13] ; D6    ; 8        ; 9            ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[14] ; A7    ; 8        ; 20           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[15] ; C6    ; 8        ; 18           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[16] ; C8    ; 8        ; 23           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[17] ; E6    ; 8        ; 14           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[18] ; E7    ; 8        ; 16           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[19] ; D8    ; 8        ; 23           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[1]  ; C3    ; 8        ; 1            ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[20] ; E8    ; 8        ; 20           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[21] ; F8    ; 8        ; 20           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[22] ; F9    ; 7        ; 34           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[23] ; E9    ; 7        ; 29           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[24] ; C9    ; 7        ; 31           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[25] ; D9    ; 7        ; 31           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[26] ; E11   ; 7        ; 45           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[27] ; E10   ; 7        ; 45           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[28] ; C11   ; 7        ; 38           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[29] ; B11   ; 7        ; 40           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[2]  ; A2    ; 8        ; 7            ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[30] ; A12   ; 7        ; 43           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[31] ; D11   ; 7        ; 51           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[32] ; D12   ; 7        ; 51           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[33] ; B12   ; 7        ; 43           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[3]  ; A3    ; 8        ; 7            ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[4]  ; B3    ; 8        ; 3            ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[5]  ; B4    ; 8        ; 7            ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[6]  ; A4    ; 8        ; 9            ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[7]  ; B5    ; 8        ; 11           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[8]  ; A5    ; 8        ; 14           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_0_D[9]  ; D5    ; 8        ; 5            ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[0]  ; F13   ; 6        ; 53           ; 21           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[10] ; P11   ; 4        ; 38           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[11] ; R10   ; 4        ; 34           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[12] ; N12   ; 4        ; 47           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[13] ; P9    ; 4        ; 38           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[14] ; N9    ; 4        ; 29           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[15] ; N11   ; 4        ; 43           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[16] ; L16   ; 5        ; 53           ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[17] ; K16   ; 5        ; 53           ; 12           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[18] ; R16   ; 5        ; 53           ; 8            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[19] ; L15   ; 5        ; 53           ; 11           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[1]  ; T15   ; 4        ; 45           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[20] ; P15   ; 5        ; 53           ; 6            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[21] ; P16   ; 5        ; 53           ; 7            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[22] ; R14   ; 4        ; 49           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[23] ; N16   ; 5        ; 53           ; 9            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[24] ; N15   ; 5        ; 53           ; 9            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[25] ; P14   ; 4        ; 49           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[26] ; L14   ; 5        ; 53           ; 9            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[27] ; N14   ; 5        ; 53           ; 6            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[28] ; M10   ; 4        ; 43           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[29] ; L13   ; 5        ; 53           ; 10           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[2]  ; T14   ; 4        ; 45           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[30] ; J16   ; 5        ; 53           ; 14           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[31] ; K15   ; 5        ; 53           ; 13           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[32] ; J13   ; 5        ; 53           ; 16           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[33] ; J14   ; 5        ; 53           ; 15           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[3]  ; T13   ; 4        ; 40           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[4]  ; R13   ; 4        ; 40           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[5]  ; T12   ; 4        ; 36           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[6]  ; R12   ; 4        ; 36           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[7]  ; T11   ; 4        ; 36           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[8]  ; T10   ; 4        ; 34           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; GPIO_1_D[9]  ; R11   ; 4        ; 34           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                        ;
+----------+------------------------------------------+-------------------+------------------+---------------------------+
; Location ; Pin Name                                 ; Reserved As       ; User Signal Name ; Pin Type                  ;
+----------+------------------------------------------+-------------------+------------------+---------------------------+
; F4       ; nSTATUS                                  ; -                 ; -                ; Dedicated Programming Pin ;
; H5       ; nCONFIG                                  ; -                 ; -                ; Dedicated Programming Pin ;
; J3       ; nCE                                      ; -                 ; -                ; Dedicated Programming Pin ;
; J16      ; DIFFIO_R9n, DEV_OE                       ; Use as regular IO ; GPIO_1_D[30]     ; Dual Purpose Pin          ;
; J15      ; DIFFIO_R9p, DEV_CLRn                     ; Use as regular IO ; KEY[0]           ; Dual Purpose Pin          ;
; H14      ; CONF_DONE                                ; -                 ; -                ; Dedicated Programming Pin ;
; H13      ; MSEL0                                    ; -                 ; -                ; Dedicated Programming Pin ;
; H12      ; MSEL1                                    ; -                 ; -                ; Dedicated Programming Pin ;
; G12      ; MSEL2                                    ; -                 ; -                ; Dedicated Programming Pin ;
; G12      ; MSEL3                                    ; -                 ; -                ; Dedicated Programming Pin ;
; B11      ; DIFFIO_T20p, PADD0                       ; Use as regular IO ; GPIO_0_D[29]     ; Dual Purpose Pin          ;
; A15      ; DIFFIO_T19n, PADD1                       ; Use as regular IO ; LED[0]           ; Dual Purpose Pin          ;
; F9       ; DIFFIO_T17p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO ; GPIO_0_D[22]     ; Dual Purpose Pin          ;
; C9       ; DIFFIO_T15n, PADD7                       ; Use as regular IO ; GPIO_0_D[24]     ; Dual Purpose Pin          ;
; D9       ; DIFFIO_T15p, PADD8                       ; Use as regular IO ; GPIO_0_D[25]     ; Dual Purpose Pin          ;
; E9       ; DIFFIO_T13p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO ; GPIO_0_D[23]     ; Dual Purpose Pin          ;
; C8       ; DIFFIO_T11p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; GPIO_0_D[16]     ; Dual Purpose Pin          ;
; E8       ; DIFFIO_T10n, DATA2                       ; Use as regular IO ; GPIO_0_D[20]     ; Dual Purpose Pin          ;
; F8       ; DIFFIO_T10p, DATA3                       ; Use as regular IO ; GPIO_0_D[21]     ; Dual Purpose Pin          ;
; A7       ; DIFFIO_T9n, PADD18                       ; Use as regular IO ; GPIO_0_D[14]     ; Dual Purpose Pin          ;
; B7       ; DIFFIO_T9p, DATA4                        ; Use as regular IO ; GPIO_0_D[12]     ; Dual Purpose Pin          ;
; A6       ; DIFFIO_T7n, DATA14, DQS3T/CQ3T#,DPCLK11  ; Use as regular IO ; GPIO_0_D[11]     ; Dual Purpose Pin          ;
; B6       ; DIFFIO_T7p, DATA13                       ; Use as regular IO ; GPIO_0_D[10]     ; Dual Purpose Pin          ;
; E7       ; DATA5                                    ; Use as regular IO ; GPIO_0_D[18]     ; Dual Purpose Pin          ;
; E6       ; DIFFIO_T6p, DATA6                        ; Use as regular IO ; GPIO_0_D[17]     ; Dual Purpose Pin          ;
; A5       ; DIFFIO_T5n, DATA7                        ; Use as regular IO ; GPIO_0_D[8]      ; Dual Purpose Pin          ;
; B5       ; DIFFIO_T5p, DATA8                        ; Use as regular IO ; GPIO_0_D[7]      ; Dual Purpose Pin          ;
; D6       ; DIFFIO_T4n, DATA9                        ; Use as regular IO ; GPIO_0_D[13]     ; Dual Purpose Pin          ;
; A4       ; DIFFIO_T3n, DATA10                       ; Use as regular IO ; GPIO_0_D[6]      ; Dual Purpose Pin          ;
; B4       ; DIFFIO_T3p, DATA11                       ; Use as regular IO ; GPIO_0_D[5]      ; Dual Purpose Pin          ;
; B3       ; DATA12, DQS1T/CQ1T#,CDPCLK7              ; Use as regular IO ; GPIO_0_D[4]      ; Dual Purpose Pin          ;
+----------+------------------------------------------+-------------------+------------------+---------------------------+


+-------------------------------------------------------------+
; I/O Bank Usage                                              ;
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1        ; 4 / 14 ( 29 % )   ; 3.3V          ; --           ;
; 2        ; 2 / 16 ( 13 % )   ; 3.3V          ; --           ;
; 3        ; 2 / 25 ( 8 % )    ; 3.3V          ; --           ;
; 4        ; 20 / 20 ( 100 % ) ; 3.3V          ; --           ;
; 5        ; 17 / 18 ( 94 % )  ; 3.3V          ; --           ;
; 6        ; 1 / 13 ( 8 % )    ; 3.3V          ; --           ;
; 7        ; 17 / 24 ( 71 % )  ; 3.3V          ; --           ;
; 8        ; 24 / 24 ( 100 % ) ; 3.3V          ; --           ;
+----------+-------------------+---------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                              ;
+----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; A1       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; A2       ; 238        ; 8        ; GPIO_0_D[2]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A3       ; 239        ; 8        ; GPIO_0_D[3]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A4       ; 236        ; 8        ; GPIO_0_D[6]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A5       ; 232        ; 8        ; GPIO_0_D[8]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A6       ; 225        ; 8        ; GPIO_0_D[11]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A7       ; 220        ; 8        ; GPIO_0_D[14]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A8       ; 211        ; 8        ; GPIO_0_IN[0]                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A9       ; 209        ; 7        ; GND+                            ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; A10      ; 198        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A11      ; 188        ; 7        ; LED[3]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A12      ; 186        ; 7        ; GPIO_0_D[30]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A13      ; 179        ; 7        ; LED[1]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A14      ; 181        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A15      ; 191        ; 7        ; LED[0]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A16      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; B1       ; 5          ; 1        ; LED[6]                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; B2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B3       ; 242        ; 8        ; GPIO_0_D[4]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B4       ; 237        ; 8        ; GPIO_0_D[5]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B5       ; 233        ; 8        ; GPIO_0_D[7]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B6       ; 226        ; 8        ; GPIO_0_D[10]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B7       ; 221        ; 8        ; GPIO_0_D[12]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B8       ; 212        ; 8        ; GPIO_0_IN[1]                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B9       ; 210        ; 7        ; SW[2]                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B10      ; 199        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B11      ; 189        ; 7        ; GPIO_0_D[29]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B12      ; 187        ; 7        ; GPIO_0_D[33]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B13      ; 180        ; 7        ; LED[2]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B14      ; 182        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B16      ; 164        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C3       ; 245        ; 8        ; GPIO_0_D[1]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C4       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C5       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C6       ; 224        ; 8        ; GPIO_0_D[15]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C7       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C8       ; 215        ; 8        ; GPIO_0_D[16]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C9       ; 200        ; 7        ; GPIO_0_D[24]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C10      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C11      ; 190        ; 7        ; GPIO_0_D[28]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C12      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C13      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C14      ; 175        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C15      ; 174        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C16      ; 173        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D1       ; 10         ; 1        ; LED[4]                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; D2       ; 9          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D3       ; 246        ; 8        ; GPIO_0_D[0]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D4       ;            ;          ; VCCD_PLL3                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; D5       ; 241        ; 8        ; GPIO_0_D[9]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D6       ; 234        ; 8        ; GPIO_0_D[13]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D8       ; 216        ; 8        ; GPIO_0_D[19]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D9       ; 201        ; 7        ; GPIO_0_D[25]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D11      ; 177        ; 7        ; GPIO_0_D[31]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D12      ; 178        ; 7        ; GPIO_0_D[32]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D13      ;            ;          ; VCCD_PLL2                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; D14      ; 176        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D15      ; 170        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D16      ; 169        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E1       ; 26         ; 1        ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E3       ;            ; 1        ; VCCIO1                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; E4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E5       ;            ;          ; GNDA3                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E6       ; 231        ; 8        ; GPIO_0_D[17]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E7       ; 227        ; 8        ; GPIO_0_D[18]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E8       ; 218        ; 8        ; GPIO_0_D[20]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E9       ; 205        ; 7        ; GPIO_0_D[23]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E10      ; 184        ; 7        ; GPIO_0_D[27]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E11      ; 183        ; 7        ; GPIO_0_D[26]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E12      ;            ;          ; GNDA2                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E14      ;            ; 6        ; VCCIO6                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; E15      ; 151        ; 6        ; GND+                            ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; E16      ; 150        ; 6        ; GND+                            ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; F1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F2       ; 13         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F3       ; 8          ; 1        ; LED[5]                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F4       ; 11         ; 1        ; ^nSTATUS                        ;        ;              ;         ; --         ;                 ; --       ; --           ;
; F5       ;            ; --       ; VCCA3                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F6       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F8       ; 219        ; 8        ; GPIO_0_D[21]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; F9       ; 197        ; 7        ; GPIO_0_D[22]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; F10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F12      ;            ; --       ; VCCA2                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F13      ; 161        ; 6        ; GPIO_1_D[0]                     ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F14      ; 167        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; F15      ; 163        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F16      ; 162        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G3       ;            ; 1        ; VCCIO1                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; G4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G5       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G8       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G9       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G10      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G11      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G12      ; 155        ; 6        ; ^MSEL2                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
; G12      ; 156        ; 6        ; ^MSEL3                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
; G13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G14      ;            ; 6        ; VCCIO6                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; G15      ; 160        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G16      ; 159        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H1       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; --       ; On           ;
; H2       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H3       ; 21         ; 1        ; #TCK                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; H4       ; 20         ; 1        ; #TDI                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; H5       ; 19         ; 1        ; ^nCONFIG                        ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; H7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H9       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; H12      ; 154        ; 6        ; ^MSEL1                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H13      ; 153        ; 6        ; ^MSEL0                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H14      ; 152        ; 6        ; ^CONF_DONE                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H16      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J1       ; 30         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J2       ; 29         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J3       ; 24         ; 1        ; ^nCE                            ;        ;              ;         ; --         ;                 ; --       ; --           ;
; J4       ; 23         ; 1        ; #TDO                            ; output ;              ;         ; --         ;                 ; --       ; --           ;
; J5       ; 22         ; 1        ; #TMS                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; J6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J9       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J11      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J12      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J13      ; 146        ; 5        ; GPIO_1_D[32]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J14      ; 144        ; 5        ; GPIO_1_D[33]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J15      ; 143        ; 5        ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J16      ; 142        ; 5        ; GPIO_1_D[30]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K1       ; 37         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K2       ; 36         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K3       ;            ; 2        ; VCCIO2                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; K4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K5       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K6       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K9       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K10      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K12      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K14      ;            ; 5        ; VCCIO5                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; K15      ; 141        ; 5        ; GPIO_1_D[31]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K16      ; 140        ; 5        ; GPIO_1_D[17]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L1       ; 39         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L2       ; 38         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L3       ; 40         ; 2        ; LED[7]                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L5       ;            ; --       ; VCCA1                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; L7       ; 75         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; L8       ; 79         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; L9       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L11      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L12      ;            ; --       ; VCCA4                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L13      ; 136        ; 5        ; GPIO_1_D[29]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L14      ; 134        ; 5        ; GPIO_1_D[26]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L15      ; 138        ; 5        ; GPIO_1_D[19]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L16      ; 137        ; 5        ; GPIO_1_D[16]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M1       ; 28         ; 2        ; SW[0]                           ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M2       ; 27         ; 2        ; GND+                            ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; M3       ;            ; 2        ; VCCIO2                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; M4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M5       ;            ;          ; GNDA1                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M6       ; 64         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; M7       ; 68         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; M8       ; 81         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; M9       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M10      ; 111        ; 4        ; GPIO_1_D[28]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M12      ;            ;          ; GNDA4                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M14      ;            ; 5        ; VCCIO5                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; M15      ; 149        ; 5        ; SW[3]                           ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M16      ; 148        ; 5        ; GND+                            ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; N1       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N2       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N3       ; 52         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; N4       ;            ;          ; VCCD_PLL1                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N5       ; 62         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; N6       ; 63         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; N7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N8       ; 82         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; N9       ; 93         ; 4        ; GPIO_1_D[14]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N11      ; 112        ; 4        ; GPIO_1_D[15]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N12      ; 117        ; 4        ; GPIO_1_D[12]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N13      ;            ;          ; VCCD_PLL4                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N14      ; 126        ; 5        ; GPIO_1_D[27]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; N15      ; 133        ; 5        ; GPIO_1_D[24]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; N16      ; 132        ; 5        ; GPIO_1_D[23]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; P1       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P2       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P3       ; 53         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; P4       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P5       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P6       ; 67         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; P7       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P8       ; 85         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; P9       ; 105        ; 4        ; GPIO_1_D[13]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P10      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P11      ; 106        ; 4        ; GPIO_1_D[10]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P12      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P13      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P14      ; 119        ; 4        ; GPIO_1_D[25]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P15      ; 127        ; 5        ; GPIO_1_D[20]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; P16      ; 128        ; 5        ; GPIO_1_D[21]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; R1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R3       ; 54         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R4       ; 60         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R5       ; 71         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R6       ; 73         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R7       ; 76         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R8       ; 86         ; 3        ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R9       ; 88         ; 4        ; GPIO_1_IN[1]                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R10      ; 96         ; 4        ; GPIO_1_D[11]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R11      ; 98         ; 4        ; GPIO_1_D[9]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R12      ; 100        ; 4        ; GPIO_1_D[6]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R13      ; 107        ; 4        ; GPIO_1_D[4]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R14      ; 120        ; 4        ; GPIO_1_D[22]                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R16      ; 129        ; 5        ; GPIO_1_D[18]                    ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; T1       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; T2       ; 59         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T3       ; 55         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T4       ; 61         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T5       ; 72         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T6       ; 74         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T7       ; 77         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T8       ; 87         ; 3        ; SW[1]                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T9       ; 89         ; 4        ; GPIO_1_IN[0]                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T10      ; 97         ; 4        ; GPIO_1_D[8]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T11      ; 99         ; 4        ; GPIO_1_D[7]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T12      ; 101        ; 4        ; GPIO_1_D[5]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T13      ; 108        ; 4        ; GPIO_1_D[3]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T14      ; 115        ; 4        ; GPIO_1_D[2]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T15      ; 116        ; 4        ; GPIO_1_D[1]                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T16      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                   ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name         ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+
; |DE0_NANO                  ; 82 (48)     ; 47 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 87   ; 0            ; 35 (21)      ; 0 (0)             ; 47 (27)          ; |DE0_NANO                   ; work         ;
;    |VGA_DRIVER:driver|     ; 34 (34)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 20 (20)          ; |DE0_NANO|VGA_DRIVER:driver ; work         ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                          ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Name         ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; LED[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LED[7]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; KEY[1]       ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; SW[0]        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; SW[1]        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; SW[2]        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; SW[3]        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_IN[0] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_IN[1] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_IN[0] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_IN[1] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[0]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[1]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[2]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[3]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[4]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[6]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[8]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[10] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[12] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[14] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[16] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[18] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[20] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[22] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[24] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[25] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[26] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[27] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[28] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[29] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[30] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[31] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[32] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[33] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[0]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[1]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[2]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[3]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[4]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[5]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[6]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[7]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[8]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[9]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[10] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[11] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[12] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[13] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[14] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[15] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[16] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[17] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[18] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[19] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[20] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[21] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[22] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[23] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[24] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[25] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[26] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[27] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[28] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[29] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[30] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[31] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[32] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_1_D[33] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[5]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[7]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[9]  ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[11] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[13] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[15] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[17] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[19] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[21] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; GPIO_0_D[23] ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
; CLOCK_50     ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; KEY[0]       ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+


+-------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                          ;
+-------------------------------------------+-------------------+---------+
; Source Pin / Fanout                       ; Pad To Core Index ; Setting ;
+-------------------------------------------+-------------------+---------+
; KEY[1]                                    ;                   ;         ;
; SW[0]                                     ;                   ;         ;
; SW[1]                                     ;                   ;         ;
; SW[2]                                     ;                   ;         ;
; SW[3]                                     ;                   ;         ;
; GPIO_0_IN[0]                              ;                   ;         ;
; GPIO_0_IN[1]                              ;                   ;         ;
; GPIO_1_IN[0]                              ;                   ;         ;
; GPIO_1_IN[1]                              ;                   ;         ;
; GPIO_0_D[0]                               ;                   ;         ;
; GPIO_0_D[1]                               ;                   ;         ;
; GPIO_0_D[2]                               ;                   ;         ;
; GPIO_0_D[3]                               ;                   ;         ;
; GPIO_0_D[4]                               ;                   ;         ;
; GPIO_0_D[6]                               ;                   ;         ;
; GPIO_0_D[8]                               ;                   ;         ;
; GPIO_0_D[10]                              ;                   ;         ;
; GPIO_0_D[12]                              ;                   ;         ;
; GPIO_0_D[14]                              ;                   ;         ;
; GPIO_0_D[16]                              ;                   ;         ;
; GPIO_0_D[18]                              ;                   ;         ;
; GPIO_0_D[20]                              ;                   ;         ;
; GPIO_0_D[22]                              ;                   ;         ;
; GPIO_0_D[24]                              ;                   ;         ;
; GPIO_0_D[25]                              ;                   ;         ;
; GPIO_0_D[26]                              ;                   ;         ;
; GPIO_0_D[27]                              ;                   ;         ;
; GPIO_0_D[28]                              ;                   ;         ;
; GPIO_0_D[29]                              ;                   ;         ;
; GPIO_0_D[30]                              ;                   ;         ;
; GPIO_0_D[31]                              ;                   ;         ;
; GPIO_0_D[32]                              ;                   ;         ;
; GPIO_0_D[33]                              ;                   ;         ;
; GPIO_1_D[0]                               ;                   ;         ;
; GPIO_1_D[1]                               ;                   ;         ;
; GPIO_1_D[2]                               ;                   ;         ;
; GPIO_1_D[3]                               ;                   ;         ;
; GPIO_1_D[4]                               ;                   ;         ;
; GPIO_1_D[5]                               ;                   ;         ;
; GPIO_1_D[6]                               ;                   ;         ;
; GPIO_1_D[7]                               ;                   ;         ;
; GPIO_1_D[8]                               ;                   ;         ;
; GPIO_1_D[9]                               ;                   ;         ;
; GPIO_1_D[10]                              ;                   ;         ;
; GPIO_1_D[11]                              ;                   ;         ;
; GPIO_1_D[12]                              ;                   ;         ;
; GPIO_1_D[13]                              ;                   ;         ;
; GPIO_1_D[14]                              ;                   ;         ;
; GPIO_1_D[15]                              ;                   ;         ;
; GPIO_1_D[16]                              ;                   ;         ;
; GPIO_1_D[17]                              ;                   ;         ;
; GPIO_1_D[18]                              ;                   ;         ;
; GPIO_1_D[19]                              ;                   ;         ;
; GPIO_1_D[20]                              ;                   ;         ;
; GPIO_1_D[21]                              ;                   ;         ;
; GPIO_1_D[22]                              ;                   ;         ;
; GPIO_1_D[23]                              ;                   ;         ;
; GPIO_1_D[24]                              ;                   ;         ;
; GPIO_1_D[25]                              ;                   ;         ;
; GPIO_1_D[26]                              ;                   ;         ;
; GPIO_1_D[27]                              ;                   ;         ;
; GPIO_1_D[28]                              ;                   ;         ;
; GPIO_1_D[29]                              ;                   ;         ;
; GPIO_1_D[30]                              ;                   ;         ;
; GPIO_1_D[31]                              ;                   ;         ;
; GPIO_1_D[32]                              ;                   ;         ;
; GPIO_1_D[33]                              ;                   ;         ;
; GPIO_0_D[5]                               ;                   ;         ;
; GPIO_0_D[7]                               ;                   ;         ;
; GPIO_0_D[9]                               ;                   ;         ;
; GPIO_0_D[11]                              ;                   ;         ;
; GPIO_0_D[13]                              ;                   ;         ;
; GPIO_0_D[15]                              ;                   ;         ;
; GPIO_0_D[17]                              ;                   ;         ;
; GPIO_0_D[19]                              ;                   ;         ;
; GPIO_0_D[21]                              ;                   ;         ;
; GPIO_0_D[23]                              ;                   ;         ;
; CLOCK_50                                  ;                   ;         ;
; KEY[0]                                    ;                   ;         ;
;      - VGA_DRIVER:driver|line_count[9]~20 ; 0                 ; 6       ;
;      - VGA_DRIVER:driver|line_count[9]~21 ; 0                 ; 6       ;
+-------------------------------------------+-------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                              ;
+------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; Name                               ; Location           ; Fan-Out ; Usage                     ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; CLOCK_25                           ; FF_X28_Y1_N29      ; 46      ; Clock                     ; yes    ; Global Clock         ; GCLK18           ; --                        ;
; CLOCK_50                           ; PIN_R8             ; 1       ; Clock                     ; no     ; --                   ; --               ; --                        ;
; VGA_DRIVER:driver|line_count[9]~20 ; LCCOMB_X31_Y22_N30 ; 10      ; Sync. clear               ; no     ; --                   ; --               ; --                        ;
; VGA_DRIVER:driver|line_count[9]~21 ; LCCOMB_X27_Y30_N6  ; 20      ; Clock enable, Sync. clear ; no     ; --                   ; --               ; --                        ;
+------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                     ;
+----------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name     ; Location      ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+----------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; CLOCK_25 ; FF_X28_Y1_N29 ; 46      ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
+----------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+-----------------------------------------------+
; Routing Usage Summary                         ;
+-----------------------+-----------------------+
; Routing Resource Type ; Usage                 ;
+-----------------------+-----------------------+
; Block interconnects   ; 60 / 71,559 ( < 1 % ) ;
; C16 interconnects     ; 1 / 2,597 ( < 1 % )   ;
; C4 interconnects      ; 17 / 46,848 ( < 1 % ) ;
; Direct links          ; 36 / 71,559 ( < 1 % ) ;
; Global clocks         ; 1 / 20 ( 5 % )        ;
; Local interconnects   ; 55 / 24,624 ( < 1 % ) ;
; R24 interconnects     ; 4 / 2,496 ( < 1 % )   ;
; R4 interconnects      ; 20 / 62,424 ( < 1 % ) ;
+-----------------------+-----------------------+


+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 7.45) ; Number of LABs  (Total = 11) ;
+--------------------------------------------+------------------------------+
; 1                                          ; 4                            ;
; 2                                          ; 1                            ;
; 3                                          ; 1                            ;
; 4                                          ; 0                            ;
; 5                                          ; 0                            ;
; 6                                          ; 0                            ;
; 7                                          ; 0                            ;
; 8                                          ; 0                            ;
; 9                                          ; 0                            ;
; 10                                         ; 0                            ;
; 11                                         ; 1                            ;
; 12                                         ; 0                            ;
; 13                                         ; 0                            ;
; 14                                         ; 1                            ;
; 15                                         ; 0                            ;
; 16                                         ; 3                            ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 0.82) ; Number of LABs  (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Clock                            ; 8                            ;
; 1 Clock enable                     ; 1                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 11.73) ; Number of LABs  (Total = 11) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 2                            ;
; 2                                            ; 3                            ;
; 3                                            ; 0                            ;
; 4                                            ; 1                            ;
; 5                                            ; 0                            ;
; 6                                            ; 0                            ;
; 7                                            ; 0                            ;
; 8                                            ; 0                            ;
; 9                                            ; 0                            ;
; 10                                           ; 0                            ;
; 11                                           ; 0                            ;
; 12                                           ; 0                            ;
; 13                                           ; 0                            ;
; 14                                           ; 0                            ;
; 15                                           ; 0                            ;
; 16                                           ; 0                            ;
; 17                                           ; 0                            ;
; 18                                           ; 0                            ;
; 19                                           ; 1                            ;
; 20                                           ; 0                            ;
; 21                                           ; 1                            ;
; 22                                           ; 0                            ;
; 23                                           ; 0                            ;
; 24                                           ; 1                            ;
; 25                                           ; 0                            ;
; 26                                           ; 1                            ;
; 27                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 4.18) ; Number of LABs  (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 4                            ;
; 2                                               ; 1                            ;
; 3                                               ; 2                            ;
; 4                                               ; 0                            ;
; 5                                               ; 0                            ;
; 6                                               ; 1                            ;
; 7                                               ; 1                            ;
; 8                                               ; 0                            ;
; 9                                               ; 1                            ;
; 10                                              ; 0                            ;
; 11                                              ; 0                            ;
; 12                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 5.00) ; Number of LABs  (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 1                            ;
; 2                                           ; 2                            ;
; 3                                           ; 4                            ;
; 4                                           ; 1                            ;
; 5                                           ; 0                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 0                            ;
; 9                                           ; 1                            ;
; 10                                          ; 0                            ;
; 11                                          ; 1                            ;
; 12                                          ; 0                            ;
; 13                                          ; 0                            ;
; 14                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 10    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 20    ;
+----------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                    ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass         ; 87        ; 0            ; 87        ; 0            ; 0            ; 87        ; 87        ; 0            ; 87        ; 87        ; 0            ; 0            ; 0            ; 0            ; 79           ; 0            ; 0            ; 79           ; 0            ; 0            ; 63           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 87        ; 0            ; 0            ;
; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable ; 0         ; 87           ; 0         ; 87           ; 87           ; 0         ; 0         ; 87           ; 0         ; 0         ; 87           ; 87           ; 87           ; 87           ; 8            ; 87           ; 87           ; 8            ; 87           ; 87           ; 24           ; 87           ; 87           ; 87           ; 87           ; 87           ; 87           ; 0         ; 87           ; 87           ;
; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; LED[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[4]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[5]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[6]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LED[7]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_IN[0]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_IN[1]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_IN[0]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_IN[1]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[0]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[1]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[2]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[3]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[4]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[6]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[8]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[10]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[12]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[14]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[16]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[18]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[20]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[22]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[24]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[25]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[26]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[27]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[28]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[29]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[30]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[31]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[32]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[33]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[0]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[1]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[2]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[3]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[4]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[5]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[6]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[7]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[8]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[9]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[10]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[11]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[12]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[13]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[14]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[15]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[16]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[17]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[18]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[19]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[20]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[21]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[22]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[23]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[24]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[25]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[26]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[27]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[28]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[29]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[30]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[31]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[32]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_1_D[33]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[5]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[7]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[9]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[11]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[13]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[15]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[17]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[19]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[21]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; GPIO_0_D[23]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+----------------------------------------------------------------------------------+
; Fitter Device Options                                                            ;
+------------------------------------------------------------------+---------------+
; Option                                                           ; Setting       ;
+------------------------------------------------------------------+---------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off           ;
; Enable device-wide reset (DEV_CLRn)                              ; Off           ;
; Enable device-wide output enable (DEV_OE)                        ; Off           ;
; Enable INIT_DONE output                                          ; Off           ;
; Configuration scheme                                             ; Active Serial ;
; Error detection CRC                                              ; Off           ;
; Enable open drain on CRC_ERROR pin                               ; Off           ;
; Enable input tri-state on active configuration pins in user mode ; Off           ;
; Configuration Voltage Level                                      ; Auto          ;
; Force Configuration Voltage Level                                ; Off           ;
; nCEO                                                             ; Unreserved    ;
; Data[0]                                                          ; Unreserved    ;
; Data[1]/ASDO                                                     ; Unreserved    ;
; Data[7..2]                                                       ; Unreserved    ;
; FLASH_nCE/nCSO                                                   ; Unreserved    ;
; Other Active Parallel pins                                       ; Unreserved    ;
; DCLK                                                             ; Unreserved    ;
+------------------------------------------------------------------+---------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 �C   ;
; High Junction Temperature ; 85 �C  ;
+---------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EP4CE22F17C6 for design "DE0_NANO"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device EP4CE10F17C6 is compatible
    Info (176445): Device EP4CE6F17C6 is compatible
    Info (176445): Device EP4CE15F17C6 is compatible
Info (169141): DATA[0] dual-purpose pin not reserved
Info (12825): Data[1]/ASDO dual-purpose pin not reserved
Info (12825): nCSO dual-purpose pin not reserved
Info (12825): DCLK dual-purpose pin not reserved
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (332104): Reading SDC File: 'DE0_NANO.SDC'
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332060): Node: CLOCK_25 was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register led_counter[0] is being clocked by CLOCK_25
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 1 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   20.000     CLOCK_50
Info (176353): Automatically promoted node CLOCK_25  File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 67
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node CLOCK_25~0 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 67
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Warning (15705): Ignored locations or region assignments to the following nodes
    Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design
    Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design
    Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design
    Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design
    Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design
    Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design
    Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
    Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y23 to location X31_Y34
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169177): 79 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at E1 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 51
    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at T8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at M15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Info (169178): Pin GPIO_0_IN[0] uses I/O standard 3.3-V LVTTL at A8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 58
    Info (169178): Pin GPIO_0_IN[1] uses I/O standard 3.3-V LVTTL at B8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 58
    Info (169178): Pin GPIO_1_IN[0] uses I/O standard 3.3-V LVTTL at T9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 62
    Info (169178): Pin GPIO_1_IN[1] uses I/O standard 3.3-V LVTTL at R9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 62
    Info (169178): Pin GPIO_0_D[0] uses I/O standard 3.3-V LVTTL at D3 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[1] uses I/O standard 3.3-V LVTTL at C3 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[2] uses I/O standard 3.3-V LVTTL at A2 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[3] uses I/O standard 3.3-V LVTTL at A3 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[4] uses I/O standard 3.3-V LVTTL at B3 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[6] uses I/O standard 3.3-V LVTTL at A4 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[8] uses I/O standard 3.3-V LVTTL at A5 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[10] uses I/O standard 3.3-V LVTTL at B6 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[12] uses I/O standard 3.3-V LVTTL at B7 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[14] uses I/O standard 3.3-V LVTTL at A7 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[16] uses I/O standard 3.3-V LVTTL at C8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[18] uses I/O standard 3.3-V LVTTL at E7 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[20] uses I/O standard 3.3-V LVTTL at E8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[22] uses I/O standard 3.3-V LVTTL at F9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[24] uses I/O standard 3.3-V LVTTL at C9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[25] uses I/O standard 3.3-V LVTTL at D9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[26] uses I/O standard 3.3-V LVTTL at E11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[27] uses I/O standard 3.3-V LVTTL at E10 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[28] uses I/O standard 3.3-V LVTTL at C11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[29] uses I/O standard 3.3-V LVTTL at B11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[30] uses I/O standard 3.3-V LVTTL at A12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[31] uses I/O standard 3.3-V LVTTL at D11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[32] uses I/O standard 3.3-V LVTTL at D12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[33] uses I/O standard 3.3-V LVTTL at B12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_1_D[0] uses I/O standard 3.3-V LVTTL at F13 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[1] uses I/O standard 3.3-V LVTTL at T15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[2] uses I/O standard 3.3-V LVTTL at T14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[3] uses I/O standard 3.3-V LVTTL at T13 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[4] uses I/O standard 3.3-V LVTTL at R13 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[5] uses I/O standard 3.3-V LVTTL at T12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[6] uses I/O standard 3.3-V LVTTL at R12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[7] uses I/O standard 3.3-V LVTTL at T11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[8] uses I/O standard 3.3-V LVTTL at T10 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[9] uses I/O standard 3.3-V LVTTL at R11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[10] uses I/O standard 3.3-V LVTTL at P11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[11] uses I/O standard 3.3-V LVTTL at R10 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[12] uses I/O standard 3.3-V LVTTL at N12 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[13] uses I/O standard 3.3-V LVTTL at P9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[14] uses I/O standard 3.3-V LVTTL at N9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[15] uses I/O standard 3.3-V LVTTL at N11 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[16] uses I/O standard 3.3-V LVTTL at L16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[17] uses I/O standard 3.3-V LVTTL at K16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[18] uses I/O standard 3.3-V LVTTL at R16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[19] uses I/O standard 3.3-V LVTTL at L15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[20] uses I/O standard 3.3-V LVTTL at P15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[21] uses I/O standard 3.3-V LVTTL at P16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[22] uses I/O standard 3.3-V LVTTL at R14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[23] uses I/O standard 3.3-V LVTTL at N16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[24] uses I/O standard 3.3-V LVTTL at N15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[25] uses I/O standard 3.3-V LVTTL at P14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[26] uses I/O standard 3.3-V LVTTL at L14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[27] uses I/O standard 3.3-V LVTTL at N14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[28] uses I/O standard 3.3-V LVTTL at M10 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[29] uses I/O standard 3.3-V LVTTL at L13 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[30] uses I/O standard 3.3-V LVTTL at J16 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[31] uses I/O standard 3.3-V LVTTL at K15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[32] uses I/O standard 3.3-V LVTTL at J13 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_1_D[33] uses I/O standard 3.3-V LVTTL at J14 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169178): Pin GPIO_0_D[5] uses I/O standard 3.3-V LVTTL at B4 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[7] uses I/O standard 3.3-V LVTTL at B5 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[9] uses I/O standard 3.3-V LVTTL at D5 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[11] uses I/O standard 3.3-V LVTTL at A6 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[13] uses I/O standard 3.3-V LVTTL at D6 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[15] uses I/O standard 3.3-V LVTTL at C6 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[17] uses I/O standard 3.3-V LVTTL at E6 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[19] uses I/O standard 3.3-V LVTTL at D8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[21] uses I/O standard 3.3-V LVTTL at F8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin GPIO_0_D[23] uses I/O standard 3.3-V LVTTL at E9 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 45
    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at J15 File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 51
Warning (169064): Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
    Info (169065): Pin GPIO_0_D[0] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[1] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[2] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[3] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[4] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[6] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[8] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[10] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[12] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[14] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[16] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[18] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[20] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[22] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[24] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[25] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[26] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[27] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[28] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[29] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[30] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[31] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[32] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[33] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_1_D[0] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[1] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[2] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[3] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[4] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[5] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[6] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[7] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[8] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[9] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[10] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[11] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[12] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[13] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[14] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[15] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[16] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[17] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[18] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[19] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[20] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[21] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[22] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[23] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[24] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[25] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[26] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[27] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[28] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[29] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[30] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[31] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[32] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_1_D[33] has a permanently disabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Info (169065): Pin GPIO_0_D[5] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[7] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[9] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[11] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[13] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[15] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[17] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[19] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[21] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Info (169065): Pin GPIO_0_D[23] has a permanently enabled output enable File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
Info (144001): Generated suppressed messages file C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 76 warnings
    Info: Peak virtual memory: 1075 megabytes
    Info: Processing ended: Mon Jun 19 20:10:14 2017
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:05


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.fit.smsg.


